A case study on the effectiveness of Wafer-Ring Multi-sites test handler to improve of Production Output

Voon Ching Khoo

Abstract


The conventional method allows testing of only one chip at a time (single-site testing). However, due to advancements in testing procedures, current test technologies are able to conduct dual-sites testing, quad-sites testing, octal-sites testing, 16-sites testing, 32-sites testing, and so on. In line with this, the multi-site testing approach is a method that increases the number of chips that can be tested in a single touch-up. This method allows more chips to be tested per hour, thus improving the testing throughput. In this research the author take the initiative to develop a multi-sites throughput model to investigate the effectiveness of multi-site testing approach on improving the testing throughput. In the case study, five multi-site configurations were applied. These configurations were single-site, quad-sites, octal-sites, ×16-sites, and ×32-sites. A hypothesis was analyzed by using one-way ANOVA and Post Hoc Test. 


Keywords


multi-site;test handler;semiconductor testing;multi-sites testing model

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